The invention relates to a voltage multiplying circuit having several stages wherein each stage includes first and second MOS transistors and first and second capacitors, with a first summing point connected directly to the source electrode of the first MOS transistor and being connected via the first capacitor to a first clock line supplying a first clock signal, with a second summing point which connects the gate electrode of the first MOS transistor directly to the drain electrode of the second MOS transistor being connected via the second capacitor to a second clock line supplying a second clock signal, and with adjacent stages being connected via the first summing point of the one stage to the drain electrode of the first MOS transistor of the other stage.
A circuit of this type is known from the article "EEPROM adapts easily to in-system changes", Electronic Design, Aug. 18, 1983, pages 189 to 196, in particular FIG. 3a. A circuit of this type is used for generating a programming and erasing voltage from electrically erasable, non-volatile memory elements (EEPROMs) above a supply voltage of 5 V and in the region of 20 V. A circuit of this type is shown in FIG. 1, and is assembled from several voltage multiplying stages H.sub.N, with three stages H.sub.N-1, H.sub.N and H.sub.N+1 being drawn. In addition, a voltage multiplying circuit of this type can contain further stages, the number of which depends on the level of the voltage to be generated.
In the following, this circuit will be described and its mode of operation in the steady state explained.
The entire circuit is designed with MOS technology, with the MOS field-effect transistors (MOS-FETs) being of the p-channel type. The voltage multiplying stages H.sub.N-1, H.sub.N and H.sub.N+1 each comprise two MOS transistors designated as T.sub.1,N-1 and T.sub.2,N-1, T.sub.1,N and T.sub.2,N, and T.sub.1,N+1 and T.sub.2,N+1 respectively, and two MOS capacitors designated as C.sub.N-1 and C.sub.B,N-1, C.sub.N and C.sub.B,N, and C.sub.B,N+1 and C.sub.B,N+1 respectively. The connection mode of these elements will now be explained with reference to stage H.sub.N. The source electrode of the first transistor T.sub.1,N is connected via a first summing piont X.sub.1,N both to the first connecting electrode of the first capacitor C.sub.N and to the source electrode of the second transistor T.sub.2,N, and additionally to the drain electrode of the first transistor T.sub.1,N-1 of the previous stage H.sub.N-1, while the drain electrode of the first transistor T.sub.1,N is connected to the first summing point X.sub.1,N+1 of the following stage H.sub.N+1. The second connecting electrode of the first capacitor C.sub.N is connected to a first clock line L.sub.1,N supplying a first clock signal .0.. Furthermore, a second summing point X.sub.2,N connecting the drain electrode of the second transistor T.sub.2,N to the gate electrode of the first transistor T.sub.1,N is connected via the second capacitor C.sub.B,N to a second clock line L.sub.2,N supplying a second clock signal .0..sub.B. Finally, the second summing point X.sub.2,N is connected to the gate electrode of the second transistor T.sub.2,N+1 of the following stage H.sub.N+1.
The input 1 is connected to the source electrode of an input transistor T.sub.0, while the drain electrode of this transistor is connected to the first summing point X.sub.1,N-1 of the first stage H.sub.N-1. The gate electrode of this transistor T.sub.0 is supplied with the clock signal .0. via a lead. The voltage to be multiplied, preferably an operating voltage V.sub.DD, is supplied to the input 1. The multiplied output voltage V.sub.HV can then be tapped at output 2.
Subsequent stages H.sub.N and H.sub.N+1 are supplied with first clock signals .0. and .0., which are in opposite phase to one another. The corresponding second clock signals .0..sub.B and .0..sub.B are also in opposite phase to one another. The voltage rise of the first clock signal .0. or .0. is usually as large as the available supply voltage, for example 5 V, while that of the second clock signal .0..sub.B or .0..sub.B is a few volts higher, for example 8.5 V, with all voltages however being negative and the reference potential being zero volts since the transistors are of the p-channel type.
As mentioned above, this voltage multiplying circuit is designed as an integrated MOS circuit with p-channel field-effect transistors, so that the substrate has the same potential as the source electrodes of these field-effect transistors. As a result, parasitic capacitances are generated between the source/drain area of each transistor and the substrate, designated in the circuit diagram according to FIG. 1 as C.sub.p.
Voltage multiplication is achieved by charges being transferred from one stage to the following stage using the first capacitors C.sub.1, C.sub.2, . . . C.sub.N, . . . , C.sub.N+m (m&gt;0), for which reason these capacitors can also be designated as pumping capacitors. Assuming the pumping capacitor C.sub.N of the stage H.sub.N receives a certain charge quantity from the pumping capacitor C.sub.N-1 of the previous stage H.sub.N-1 via the conducting first transistor T.sub.1,N-1 of the latter, with the high level (V.sub..0. =0 V) of the clock signal .0. being applied to pumping capacitor C.sub.N, and the low level (V.sub..0. =-5 V) of the clock signal .0. to the previous stage H.sub.N-1. The first transistor T.sub.1,N of the stage H.sub.N must be non-conducting, which is achieved by the second transistor of this stage H.sub.N being conducting, since its gate/source voltage is equal to that of the transistor T.sub.1,N-1. The gate/source voltage at the transistor T.sub.1,N is therefore 0 V, meaning that this transistor is in the non-conducting state. The second capacitor C.sub.B,N of stage H.sub.N is at the high level (V.sub..0.B =0 V) of the clock signal .0..sub.B at this point, while the low level (V.sub..0.B =-8.5 V) is passed to the second capacitor C.sub.B,N- 1 of the previous stage H.sub.N-1.
The voltage level of -8.5 V is generated by a voltage doubler circuit. During the charge transfer process from capacitor C.sub.N-1 to C.sub.N, the first summing point X.sub.1,N of stage H.sub.N, for example, is at a potential of approx. -5 V (and therefore also the first summing point X.sub.1,N-1 of the previous stage H.sub.N-1) and the first summing point X.sub.1,N+1 of the subsequent stage at approx. -15 V.
If the clock now switches to the next phase, the second capacitor C.sub.B,N of the stage H.sub.N is at the low level (V.sub..0.B =-8.5 V) of the clock signal .0..sub.B, such that the first transistor T.sub.1,N changes over to the conducting state. The pumping capacitor C.sub.N also receives the low level of the clock signal .0., so that the first summing point X.sub.1,N of stage H.sub.N is shifted from approx. -5 V to approx. -10 V.
The second transistor T.sub.2,N of stage H.sub.N is by contrast non-conducting, since the potential at the second summing point X.sub.2,N-1 of the previous stage H.sub.N-1 rises on account of the high level applied to the second capacitor C.sub.B,N-1, with the first transistor T.sub.1,N-1 of the previous stage H.sub.N-1 passing simultaneously to the non-conducting state. The charge of the pumping capacitor C.sub.N is therefore transferred to the pumping capacitor C.sub.N+1 of the next stage H.sub.N+1, i.e. the first summing point X.sub.1,N+1 of this next stage is also at approx. -10 V. The next clock pulse .0. now shifts the voltage level at this first summing point X.sub.1,N+1 to approx. -15 V, while the voltage level at the first summing point X.sub.1,N of stage H.sub.N drops to approx. -5 V because of this clock change. The transistors of the two stages H.sub.N+1 and H.sub.N operate in accordance with the above description.
In order to keep the voltage drop at the first transistor T.sub.1,N of stage H.sub.N as low as possible when transferring the charge from capacitor C.sub.N to capacitor C.sub.N+1, the voltage difference .DELTA.V between the first summing point X.sub.1,N and the second summing point X.sub.2,N must be greater than the sum of the threshold voltage and the threshold voltage shift. The threshold voltage shift occurs because of the substrate effect. Since the absolute values of the voltage level at the first and second summing points become ever larger from stage to stage, the voltage difference .DELTA.V must be large enough to ensure a sufficiently low voltage drop across the first transistor even with a substrate bias voltage of, for example, -20 V in the last stage. With a supply voltage V.sub.DD of 5 V, it is possible, using an integrated voltage doubler circuit for generating the second clock voltage V.sub..0.B or V.sub..0.B, to achieve a sufficient value for the voltage difference .DELTA.V.
However, if the supply voltage V.sub.DD is substantially below 5 V, for example 2 V, a sufficient voltage difference .DELTA.V cannot be generated at acceptable expense, since a large pumping capacitance would be necessary in the voltage doubler circuit. This would however be avoidable by using a voltage trebler circuit instead of a voltage doubler circuit to generate a higher clock voltage V.sub..0.B or V.sub..0.B. A solution of this type nevertheless has a number of drawbacks, since a voltage trebler circuit requires considerably more components and also more integrated and large pumping capacitors. Finally, the generation of the clock voltage V.sub..0.B and V.sub..0.B from a higher voltage also leads to an increased power consumption due to unavoidable charge transfer losses from parasitic capacitances.